I’m currently working on a project that requires DDR3 DRAM memory. While designing, I thought it would be a good idea to note down a few basic design constraints and explore the operations of common DDR3 pins. The information mentioned below is not presented with absolute guarantee and will be updated as I make progress on the project.

The topics below are fairly general and are aimed at understanding DDR3 pin operations well enough to make logical routing decisions instead of blindly following reference designs.

• Swapping Data Lines
  • Byte Swapping
  • Bit Swapping
• Data Strobe
• Data Mask
• Clock and Clock Enable
• Command Inputs (RAS, CAS, WE, and CS)
• ODT

Swapping Data Lines

While designing a PCB with DDR3 components, it’s common to encounter two or more traces that cause routing congestion and force the designer to take a longer path. This can cause signal integrity issues later in the design cycle.

To solve this issue, the DDR3 standard supports swapping connections on some of its pins. Not all pins support this feature; therefore, care should be taken to avoid incorrect connections.

Byte Swapping

DDR3 data pins are divided into multiple byte lanes, with each byte lane containing 8 data bit lines. For example, a 32-bit wide memory bus is divided into 4 byte lanes, each containing 8 data bit lines.

Commonly used DDR3 chips like the MT41K256M16TW have a 16-bit wide memory bus and thus contain 2 byte lanes. If the processing device supports a 32-bit wide memory bus, two of these 16-bit DDR3 chips can be interfaced to utilize the entire bus capacity. Another configuration is to use four 8-bit DDR3 chips to reduce cost, at the expense of board space and increased routing complexity.

As for the swapping, entire byte lanes can be swapped to reduce design complexity. For example, you can connect the processor’s byte lane 0 to the RAM’s byte lane 1, and vice versa.

Bit Swapping

In addition to byte swapping, DDR3 also allows bit swapping, which can significantly reduce routing complexity. As discussed in the byte swapping section, each byte lane has 8 bit lines. These data bit lines can be swapped within each byte lane if the designer encounters routing congestion. It’s important to note that you cannot swap bit lines across different byte lanes.

Important: When swapping bytes or bits, the associated strobe signals (DQS/DQS#) and data mask (DM) must stay with their respective byte lane. Each byte lane forms a timing group that must be kept together. It becomes clear, why its the case once you understand the function of Data-strobe and Data-mask.

Data-Strobe

Each byte lane of DDR3 has its own clock source for read/write operations in the form of differential data strobe pins (DQS/DQS#). Unlike peripherals such as flash, eMMC, and SDIO, the data rates on DDR3 are significantly higher (800-2133 MT/s) and thus require an independent clock source to avoid edge misalignment. The data strobe pins are length-matched to the data lines, and data is sampled at the edges of these data strobe signals. During write operations, the processor generates the data strobe signals and transmits the relevant data; the DDR3 chip samples the data with respect to the data strobe edges. During read operations, the DDR3 chip transmits the data strobe signals along with the data, and the processor samples the data with respect to the edges of these signals.

This technique is often called “source-synchronous clocking,” where the clock signal (DQS) travels with the data from the source, ensuring tight timing alignment.

Data-Mask

Data reads and writes on DDR3 memory are performed in bursts. For example, the MT41K256M16TW mentioned earlier has a burst length of 8. This means that whenever the processor or RAM transfers data, it does so over four data strobe clock cycles with eight edges (rising and falling). With a 32-bit data bus, this corresponds to 32 bytes (256 bits) of data transfer. Since data transfers occur in bursts, it is impossible to write data to a single byte lane without overwriting other byte lanes. To overcome this limitation, DDR3 includes a data mask signal. While writing data to RAM, if the data mask pin is high, it masks the corresponding byte lane; if the data mask pin is low, it writes to that byte lane. This is why each byte lane has its own data mask pin, normally represented by LDM (for bits 0-7) and UDM (for bits 8-15) on a 16-bit memory chip.

The data mask is used only during write operations to prevent overwriting data and is not used during reads. When reading a single byte, the processor reads the entire 32-byte burst and discards the unwanted bytes.

Clock and Clock Enable

The clock signals, commonly represented by CK/CK#, are differential clock signals responsible for all DDR3 operations except data transfer (which uses data strobes). The processor issues commands and addresses synchronously using the clock pins. The clock is generally derived from the same source as the data strobe signals with similar frequency, i.e., half of the rated transfer speed. The command and address pins are sampled on the rising edge of the clock and thus have relaxed timing constraints compared to data pins.

The clock enable pin is used to enable or disable the internal circuitry and clocks on the DRAM. The specific circuitry enabled or disabled depends on the SDRAM configuration. Taking clock enable low enables power-saving modes like pre-charge power-down and self-refresh, which are essentially different types of sleep modes with varying wake-up speeds.

Address and Bank Address

Address pins are divided into two main groups: the row/column address A[14:0] and bank address BA[2:0]. The bank address is 3 bits wide, capable of selecting 8 banks. Row/column address pins are multiplexed with other functions, and their address width varies depending on whether rows or columns are being selected. This depends on the SDRAM configuration. For example, the MT41K256M16 has 1,024 columns corresponding to A[9:0] and 32,768 rows corresponding to A[14:0].

During the ACTIVATE command, the address pins A[14:0] provide the row address. During READ/WRITE commands, address pins A[9:0] provide the column address, A10 provides the auto-precharge flag, and A12 provides the burst chop control. The address pins work in combination with command inputs (RAS#, CAS#, WE#, and CS#) to perform the required operations.

Command Inputs (RAS, CAS, WE, and CS)

RAS#, CAS#, WE#, and CS# are active-low command pins that work together to define DDR3 operations. Different combinations of these signals create specific commands such as ACTIVATE (open row), READ, WRITE, PRECHARGE (close row), and REFRESH. The CS# pin enables or disables the chip decoder—all commands are masked when CS# is high. CS# acts as the primary control line to distinguish between memory ranks in systems with multiple ranks.

ODT

ODT (On-Die Termination) enables termination resistance internal to the DDR3 SDRAM. In normal operation, it enables the termination resistance for all DQ, DQS, and DM pins. ODT can be disabled via the LOAD MODE command, which allows the user to add custom termination resistors externally. Unlike DDR4, which provides ODT for both address/command pins and data pins, the address/command pins of DDR3 must be terminated externally.

Functional DDR3 Block Diagram

MT41K256M16 256 Meg x 16 configuration

Reference: MT41K256M16TW Datasheet

DDR3 Pin Groups

Pin Group	Pins	Description
Clock	CK, CK#	System clock (differential)
Bank Address	BA[2:0]	Bank select
Address	A[14:0]	Row/column address
Data	DQ[15:0]	Data lines
Data Strobes	DQS_L/L#, DQS_U/U#	Data sampling clocks (lower and upper byte)
Data Mask	LDM, UDM	Byte masking
Control/Command	RAS#, CAS#, WE#, CS#	Define operations
Power Control	CKE, ODT, RESET#	Enable/config functions
Power	VDD, VDDQ, VSS	Power and ground
Calibration	ZQ	Impedance calibration
Reference	VREFCA, VREFDQ	Voltage reference